CPU Subsystem Verification Engineer
Company: Arm
Key Skills: Design Engineer, Verification, RTL, CPU, Subsystem, Memory Design, FPGA, Testbench Development, Debug
Roles and Responsibilities:
- Develop and execute verification strategies for CPU subsystems and associated IP.
- Verify processor subsystems including cache hierarchy, coherency, interrupt controllers, debug, trace, memory interfaces, and subsystem integration.
- Validate functional correctness, coherency, performance scenarios, and power management across CPU subsystems.
- Own verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.
- Architect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.
- Develop verification plans, test methodologies, test cases, and coverage closure strategies.
- Drive functional, code, toggle, assertion, and coverage closure.
- Debug RTL, testbench, integration, and system-level issues.
- Collaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.
- Leverage automation, scripting, and AI-assisted workflows to improve verification productivity.
- Contribute to methodology improvements, documentation, and engineering best practices.
Skills Required:
- 2-4 years of experience in CPU, subsystem, or SoC verification.
- Strong knowledge of Verilog, SystemVerilog, UVM, and modern verification methodologies.
- Understanding of Arm CPU architecture, memory hierarchy, coherency protocols, interrupts, and subsystem integration.
- Experience with C/C++, scripting, coverage closure, and RTL/testbench debugging.
- Excellent analytical, communication, and collaboration skills.
Desired Skills and Qualifications
- Experience with CHI, ACE, AMBA, GIC, RAS, or debug/trace.
- Experience with performance and power-aware verification (UPF).
- Experience with emulation, FPGA, gate-level simulation, or post-silicon validation.
- Knowledge of Arm System Architecture.
- AI-assisted verification experience.
Education: Bachelor's or Master's degree in a relevant engineering discipline.
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