Analog circuit design
Looking only for IMMEDIATE TO 1 MONTH Joiners
Location : Hyderabad
Job Responsibilities / Day-to-Day Activities
Responsibilities Will Include But Not Limited To Following
Hands-on Design of High-Speed Custom Analog/Digital, Ring Oscillators, Dividers, Bias Blocks (Voltage & Current references), in lower Fin FET technology nodes. Verification of Block Modules end-to-end: AC, Transient, Noise, PERC, EM & IR, Reliability checks, Co-Simulations of Analog + Digital (RTL) etc. Independently guide Layout Engineer & perform Post-Layout Design fix iterations. Debug functional and performance issues in simulations Flexible to take different tasks in project. Execute tasks with minimum supervision/tracking. Have accountability and ownership on blocks & tasks assigned.
Job Deliverables
Design implementation to meet PPA goals. Create and check all relevant design views using sign-off tools. Documentation as per requirement.
Qualifications & Experiences
B. Tech/M. Tech/Ph. D in Electronics/VLSI 3yrs experience in Analog & Mixed Signal Design
Expected to have experience in
Hands-on Design experience in High-Speed PHY/IO, IO receiver/transmitter, Bias Blocks (Voltage & Current references), in lower Fin FET technology nodes. Verification of Block Modules end-to-end: AC, DC, Transient, Noise, PERC, EM & IR, Reliability checks, Co-Simulations of Analog + Digital (RTL) etc. Independently guide Layout Engineer & perform Post-Layout Design fix iterations. Debug functional and performance issues in simulations Flexible to take different tasks in project. Execute tasks with minimum supervision/tracking. Have accountability and ownership on blocks & tasks assigned.
Location : Hyderabad
Job Responsibilities / Day-to-Day Activities
Responsibilities Will Include But Not Limited To Following
Hands-on Design of High-Speed Custom Analog/Digital, Ring Oscillators, Dividers, Bias Blocks (Voltage & Current references), in lower Fin FET technology nodes. Verification of Block Modules end-to-end: AC, Transient, Noise, PERC, EM & IR, Reliability checks, Co-Simulations of Analog + Digital (RTL) etc. Independently guide Layout Engineer & perform Post-Layout Design fix iterations. Debug functional and performance issues in simulations Flexible to take different tasks in project. Execute tasks with minimum supervision/tracking. Have accountability and ownership on blocks & tasks assigned.
Job Deliverables
Design implementation to meet PPA goals. Create and check all relevant design views using sign-off tools. Documentation as per requirement.
Qualifications & Experiences
B. Tech/M. Tech/Ph. D in Electronics/VLSI 3yrs experience in Analog & Mixed Signal Design
Expected to have experience in
Hands-on Design experience in High-Speed PHY/IO, IO receiver/transmitter, Bias Blocks (Voltage & Current references), in lower Fin FET technology nodes. Verification of Block Modules end-to-end: AC, DC, Transient, Noise, PERC, EM & IR, Reliability checks, Co-Simulations of Analog + Digital (RTL) etc. Independently guide Layout Engineer & perform Post-Layout Design fix iterations. Debug functional and performance issues in simulations Flexible to take different tasks in project. Execute tasks with minimum supervision/tracking. Have accountability and ownership on blocks & tasks assigned.
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