Staff/ Principal Application Engineer, Formal Verification (VC Formal)

Application engineers (AEs) drive and deploy SNPS technologies at the customers and support successful usage of the products at the customers that leads to renewals and new business.

About the Role

Lead technical deployment of VC Formal solutions at customer sites, assessing verification environments and recommending formal methodologies tailored to their design challenges. Work directly with Synopsys R&D and product engineering teams to communicate customer priorities and technical requirements that influence product roadmap, while supporting customers in applying formal verification to complex logic.

Responsibilities

• Lead technical deployment of VC Formal solutions at customer sites, assessing verification environments and recommending formal methodologies tailored to their design challenges
• Analyze customer design blocks to identify the right targets for formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking
• Diagnose root causes of tool performance issues, including state space explosion and convergence problems, then optimize formal test benches to achieve proof closure
• Develop and deliver technical training to customer teams on new VC Formal features, product updates, and formal verification best practices
• Work directly with Synopsys R&D and product engineering teams to communicate customer priorities and technical requirements that influence product roadmap
• Support customers in applying formal verification to complex logic including data path verification, math functions, and sequential equivalence across design revisions

Qualifications

• 4 to 15 years of hands-on experience in digital design verification, with deep expertise in formal verification methodologies

Required Skills

• Strong application knowledge of formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking
• Proven experience diagnosing and resolving formal tool performance issues, including convergence problems and proof optimization
• Solid understanding of RTL design, SystemVerilog, and verification test bench development
• Experience working directly with customers in a technical consulting, application engineering, or field engineering role
• Experience with VC Formal or equivalent formal verification tools is a strong plus

The Impact You Will Have

• Enable customers to find critical bugs earlier in the design cycle, reducing costly respins and time-to-market delays
• Drive adoption of formal verification methodologies that improve verification coverage and confidence across complex SoC and IP designs
• Shape the VC Formal product roadmap by translating real-world customer challenges into actionable engineering requirements
• Accelerate customer productivity by delivering training and methodologies that make formal verification accessible to teams with varying levels of expertise
• Build long-term technical relationships with leading semiconductor companies, becoming a trusted advisor on verification strategy
• Reduce tool performance bottlenecks and proof times through expert modeling and optimization, directly improving customer ROI